floating-point adder meaning in English
浮点加法器
Examples
- The data and conclusions prove that these designs are better than the original ones ; the floating - point adder is really optimized
实验证明这些设计的性能都比原有设计有所提高，达到了优化浮点加法器的目的。 - The main research area is the structure optimization of floating - point adder , which is intent to minimize the delay of floating - point addition and optimize the circuit structure
主要研究方向是优化浮点加法器结构，减小浮点加法运算的延迟，优化电路结构。 - The algorithm and its implementation of the leading zero anticipation are very vital for the performance of a high - speed floating - point adder in today s state of art microprocessor design . unfortunately , in predicting " shift amount " by a conventional lza design , the result could be off by one position . this paper presents a novel parallel error detection algorithm for a general - case lza
目前国际上已有很多算法对前导0预测算法进行了研究，但是出于设计方法和延迟等方面的限制，大部分前导0预测算法都为非精确算法，其预测结果可能与真实加法结果中前导0的个数产生一位的误差，这个误差需要在浮点加法的后规格化过程中进行修正，因此反过来又增加了浮点加减算法的关键路径延迟。 - After that , it gives the measures of designing dsp ' s assembler as a part of the dsp ' s software development environment together with the c - compiler . moreover , this paper explores the method of design the floating - point arithmetic unit . referring to the ieee754 - 1985 standard for binary floating - point arithmetic , the algorithm and the behavior description of floating - point adder and multiplier is given , and the simulation and verification is shown at the end of this paper
此外，本文还对处理器的浮点运算单元设计做了初步的研究，以ansi ieee - 754浮点数二进制标准为参考，借鉴了经典的定点加法器和乘法器的设计，尝试性的给出了浮点加法单元和乘法单元的实现模型和行为级上的硬件描述，并对其进行仿真和验证。